Digital signal generator using digital differential analyzer techniques

ABSTRACT

A signal generator capable of generating triangular and sine functions in a bipolar mode. The combination of a counter, adder and accumulator register make up a computing unit which is controlled by timing pulses added accumulatively. When an accumulator register fills, the overflow pulses are accumulated in another register. By combining the outputs of the various registers, the desired functions are produced.

United States Patent Inventor Bernard P. Wenzl China Lake. Calif. Appl, No. 819,874 Filed Apr. 28, 1969 Patented June 29, 1971 Assignee The United States 01 America as represented by the Secretary of the Navy DIGITAL SIGNAL GENERATOR USING DIGITAL DIFFERENTIAL ANALYZER TECHNIQUES 2 Claims, 7 Drawing Figs.

US. Cl 235/197, 235/150.31,235/150.53 Int. Cl .1 G06g 7/26, 1 G06j 1/02 Field of Search 235/197,

FOURTN [cosine DuYPuv REGISTER I ACCUIULATOR L uP DOIN C'Oult'ln [561 References Cited UNITED STATES PATENTS 3,027,078 3/1962 Steele 235/150.31 3,119,928 1/1964 Skramstad.... 235/150.52 X 3,139,522 6/1964 Voles 235/150.31 3,148,273 9/1964 Truitt et a1.... 235/l50.31 3,490,019 1/1970 lessen et a1. 235/15031 X Primary Examiner-Malcolm A. Morrison Assistant Examiner-Joseph F. Ruggiero Aztorneys-Edgar J. Brower and Roy Miller ABSTRACT: A signal generator capable of generating triangular and sine functions in a bipolar mode. The combination of a counter, adder and accumulator register make up a computing unit which is controlled by timing pulses added accumulatively. When an accumulator register fills, the overflow pulses are accumulated in another register. By combining the outputs of the various registers, the desired functions are produced.

ZERO DEYECT HIP-norm ONTROL) cesm: AMPLITUDE 1 CONTROL SUIICNES lERO DEYEOT (UR-DOWN CONTROL) FIRST ACCUHULAYOR career I .11 I

IECOIB l CCUIU LAYOR TNIRD i Aeeuluufmt SINE AMPLITUDE j CONTROL SWITCHES 5m: OUTPUT REGISYET] PATENTEU JUN29 |97| SHEET 2 [IF 4 ZERO DETECT (UP-DOWN CONTROL) FOURTH cosmE OUTPUT REGISTER I ACOUMULATOR I UP DOWN COUNTER I I I l7 l8 ZERO DETECT (UP -oowcomnou 20 /l6 COSINE AMPLITUDE CONTROL SWITCHES J x COSINE FIRST DOWN COUNTER ACCUMULATOR I l3 ZERO DETECT sEcoNo .ACCUMULATOR UP COUNTER FIG. 4.

THIRD ACCUN ULATOR s u E o U'rPU T EEEIETER UP-DOWN COUNTER PATENTED M2919?! K FIG. 7.

SHEET u UF 4 2, REGISTER '3 l4 FIG. 6.

/l2 SECOND AccuuuLnER n REGIsTER 2| Z l5 I v 1 AMPLITUDE 25 I CONTROL SWITCHES 24 22 23 THIRD 1 l P R AccuuuLA'roR OUT UT TE Z 3 FULL counr 0 Y REGISTER n n Y Y" COUNTI A ZERO count up up up UP 7 602 AMPL. CONTROL I SWITCH SETTING 1 i I Y REGISTER I 1 (TRIANGULAR 1 OUTPUT Y Y I coum'me B ZERO COUNT UP oovm xzwt DIGITAL SIGNAL GENERATOR USING DIGITAL DIFFERENTIAL ANALYZER TECHNIQUES GOVERNMENT INTEREST The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION One technique used to obtain a digital representation of a sine wave is sampling. An analog signal is sampled and the sample applied to a digital to analog converter. The resulting output is a digital number or level corresponding to the amplitude of the sine wave at the time the sample was taken. The accuracy of this technique is severely limited, however, by the sample, the accuracy of available digital to analog converters and the noise present in the analog signal. lt-is apparent that the sampling technique requires a large number of samples per cycle to faithfully reproduce a sine wave in digital form.

SUMMARY OF THE INVENTION In accordance with the present invention, digital differential analyzer techniques are used to generate sine cosine and triangular functions. The combination of a counter, adder and accumulator register make up the computing unit of a digital differential analyzer. The computing units which can be composed of any ofa number of digital integrated or discrete com ponent circuits such as Texas Instruments J-K Flip-Flops, and, where required, negative AND gates are in turn controlled by timing pulses, and with each pulse the contents of the counter are added cumulatively to the contents of the register. The register fills up and puts out an overflow or carry. The overflow pulses from various registers are then combined to produce sine and cosine functions.

BRIEF DESCRIPTION OF THE DRAWING FIG, I is a graph of rectangular integration of the function y=fAQ FIG. 2 is a block diagram of a basic digital differential analyzer;

FIG. 3 is a block diagram ofa digital sine and cosine generator;

FIG. 4 is a block diagram ofa digital sine and cosine generator having amplitude control;

FIG. 5 is a graph showing various waveforms of the generator shown in FIG. 4;

FIG. 6 is a block diagram of a digital triangular wave generator; and

FIG. 7 is a graph showing various waveforms of the generator shown in FIG. 6.

DESCRIPTION OF THE PREFERRED EMBODIMENT The integral ofa function y=f(x) is represented by the area bounded by the curve of the function. By the integration method of Euler, the integral can be approximated by the sum of the areas ofincremental rectangles under the curve.

Referring to FIG. 1, if y is the height of the incremental rectangles and Ar is the width of the incremental rectangles, the value of the integral is:

where y is the initial value of y=f(x) and Ax x, is an increment ofthe independent variable.

If we assume that the incremental value of the independent variable is AFI, the expression for the integral of equation l becomes:

1.! A: y.-+un

To calculate the value of the integral, it becomes sufficient to sum the heights of all the rectangles ofunit width.

The ordinate values of the rectangle may be represented as:

I ya yo-l- M From equations (3) and (4) with Ax, =1, it can be seen that the block diagram shown in FIG. 2 will implement the integration. Consider the function dz=ydx. Integrating both sides we obtain:

from equation (4).

Since Axis also unity in a digital system, each time a Ax pulse is received, y, is gated by gate 11 to register 10. If register 10 is an accumulator, as shown, y, is added or accumulated to register 10. Accumulator register 10 then accumulates the product y, Ax=y, where Ax=l. The accumulation of these products forms from equation (3). Binary multiplication normally requires a double-length register, however, since true multiplication is not being performed, the use of a double-length accumulator register can be avoided.

Since Ax=l the product y,- Ax equals y, and the accumulator register need only be as long as the counter to receive the minor product y, Ax. However, as successive products of y, Ax are accumulated, the accumulator must overflow. The over- 7 flow will be a carry from the minor part of the product into the major part. In this binary system, the carry can only be one, and the major part can change at most by one with each clock pulse.

Referring 'to FIG. 3 if counter 13 receives these carries as A the counter will form the sum from equation (4).

Substituting (6) and (7) into (8) and (9);

du cosine xi:

du sine xix The implementation of equations (10) and (II) is shown in FIG. 3, where the counting of du and du forms u sine x and u: =cos x respectively. The negative sign for du -u, dx is taken care of by making counter 13 a down counter. To account for initial conditions, cosine register 13 would have to be maximum initially and sine register 12 zero initially.

In order to minimize error, the program is reset at the end of each quarter cycle and only quarter waves are generated. Since only quarter waves are generated, sine counter 12 is an up counter and cosine counter 13 is a down counter. The quarter waves generated are put together using appropriate switching to form full cycles.

Due to the fact that the output pulses of first accumulator 10 are used as the input to cosine down counter 13, and the output of second accumulator is used as the input to sine up counter 12, an error results. This error is known as roundoff error. Studies have shown that the magnitude of the roundoff error reaches unacceptable limits after the computation of only a few values of the sine and cosine function. However, if a permanent bias is set into first and second accumulator registers 10 and 15, the magnitude of the roundoff error is affected considerably. By preloading an initial value into each of these registers of one-half their maximum capacity, the average value of the roundoff error is reduced to zero.

The error remaining after this roundoff error correction is known as the truncation error, which arises from the fact that the Euler forms of integration results in summing a series of crude approximations in order to compute successive values of the function. Studies, undertaken with the aid of a digital computer, indicate that a 14-bit sine function can be generated from O to 1r/2 radians, with an error not exceeding the value of the least significant bit, if the roundoff correction is incorporated into the system.

In addition to preloading accumulator registers 10 and 15, cosine register 13 must be preloaded to its maximum value. With each carry from first accumulator 10, cosine register 13 counts down until a zero count is reached. When a zero is detected in cosine register 13, a detect pulse can be obtained each quarter cycle as the cosine goes to zero. This detect pulse can be used to set sine and cosine registers 12 and 13 to their initial conditions, to switch the inputs to an up-down counter from du to du and to switch said up-down counter from count up to count down or vice versa every quarter cycle. Simultaneously, sine register 12, which has an initial count of zero, counts up with each carry from second accumulator 15 until a maximum count is reached. At this time, sine and cosine registers 12 and 13, and first and second accumulator 10 and 15 are reset to their initial conditions and the sequence is repeated.

Amplitude control of the generated functions is attained through the use of additional computing units 16 and 21 as shown in FIG. 4.

The desired maximum amplitude is set on cosine amplitude control switch and sine amplitude control switch 25. With each carry, the contents of switches 20 and 2S are accumulated in fourth accumulator l7 and third accumulator 22, respectively. When registers 17 and 22 fill up, they generate a spillover or carry, causing cosine output register up-down counter 18 and sine output register up-down counter 23 to count up or down, whichever is required. The result is that the maximum amplitude generated will equal the setting on the switches.

In addition to controlling amplitude, the fact that counters 18 and 23 are commanded to count up at certain times, and down at other times, results in producing continuous sine and cosine functions as shown in FIG. 5.

FIG. 5A shows the output of cosine down counter 13. Every quarter cycle counter 13 is reset to its maximum value. FIG. 5B shows the output of sine up counter 12. Every quarter cycle counter 12 is reset to zero. The abscissa of FIG. 5 is x=w1 When a zero is detected in cosine register 13, a zero detect" pulse is obtained each quarter cycle. This zero detect" pulse actuates switching network 26 so that: the output of first accumulator 10 is fed to gate 19 and the output of second accumulator I5 is fed to gate 24 during the first and third quarters of a cycle; and the output of first accumulator 10 is fed to gate 24 and the output of second accumulator 15 is fed to gate 19 during the second and fourth quarters of a cycle. In addition, a zero detect" on the output of register 18 reverses the up-down sequence of counter 23; and a zero detect" on the output of register 23 reverses the up-down sequence of counter 18. The outputs of registers 18 and 23 are shown in FIGS. 5C and 5D respectively.

In order to generate one cycle approximately 100,000 computations must be made. The frequency of the function generated can therefore be varied by controlling the rate at which computations are made by changing the frequency of the dx pulses into gates 11 and 14, the frequency of the output can be changed.

A digital triangular function generator can be produced by arranging the computing units as shown in FIG. 6.

An initial value of .707 is preset into 2,, register 13, resulting in an input to gate 24 of pulses having a rate 0.707 times that of timing pulses dx into gate 14. This results in a function having a period the same as the sine wave previously considered. Therefore,- the same frequency control network that was used for the sine and cosine functions can be used here.

Referring to FIG. 7, the triangular function waveforms are shown. The abscissa of the graphs is x=wt. FIG. 7A shows the output of Y,, register 12. Note that at the end of each carry, register 12 is reset to zero. FIG. 7B shows the output of register 23. Note that after appropriate switching, via gate 24, a triangular waveform 15 produced.

What I claim is:

1. A digital signal generator comprising:

clock means;

a first accumulator register having a serial output and a parallel input;

an up counter having a parallel output and a serial input;

means for gating the parallel output of the up counter to the parallel input of the first accumulator register in response to the clock means;

a second accumulator register having a parallel input and an output serially connected to the input of the up counter;

' a down counter having a parallel output and an input serially connected to the output of the first accumulator register;

means for gating the parallel output of the down counter to the parallel input of the second accumulator register in response to the clock means; so that a quadrant of a sine wave will appear at the parallel output of the up counter and a quadrant of a cosine wave will appear at the parallel output of the down counter;

first amplitude control means for producing a first preset amplitude;

a third accumulated register having a parallel input and a serial output;

means for detecting when the parallel output of the down counter is zero;

means for gating the output of the first amplitude control means to the parallel input of the third accumulator register in alternate response to;

the serial output of the second accumulator register until the parallel output of the down counter reaches zero, and the serial output of the first accumulator register until the parallel output of the down counter reaches zero.

a first up-down counter having a parallel output and an input serially connected to the output of the third accumulator register;

second amplitude control means for producing a second preset amplitude;

a fourth accumulator register having a parallel input and a serial output;

means for gating the output of the second amplitude control means to the parallel input of the fourth accumulator register in alternate response to;

the serial output of the first accumulator register until the parallel output of the down counter reaches zero, and the serial output of the second accumulator register until the parallel output of the down counter reaches zero;

a second up-down counter having a parallel output and an input serially connected to the output of the fourth accumulator register;

means for detecting a zero at the output of the second updown counter;

means for reversing the up-down mode of the first up-down 2. A digital signal generator as set forth in claim 1 and further including:

means for disconnecting the serial input to the down counter; and

means for constantly loading the down counter so that the serial output of the second accumulator is 0.707 times the clock rate;

to produce a triangular wave at the parallel output of the first up-down counter. 

1. A digital signal generator comprising: clock means; a first accumulator register having a serial output and a parallel input; an up counter having a parallel output and a serial input; means for gating the parallel output of the up counter to the parallel input of the first accumulator register in response to the clock means; a second accumulator register having a parallel input and an output serially connected to the input of the up counter; a down counter having a parallel output and an input serially connected to the output of the first accumulator register; means for gating the parallel output of the down counter to the parallel input of the second accumulator register in response to the clock means; so that a quadrant of a sine wave will appear at the parallel output of the up counter and a quadrant of a cosine wave will appear at the parallel output of the down counter; first amplitude control means for producing a first preset amplitude; a third accumulated register having a parallel input and a serial output; means for detecting when the parallel output of the down counter is zero; means for gating the output of the first amplitude control means to the parallel input of the third accumulator register in alternate response to; the serial output of the second accumulator register until the parallel output of the down counter reaches zero, and the serial output of the first accumulator register until the parallel output of the down counter reaches zero; a first up-down counter having a parallel output and an input serially connected to the output of the third accumulator register; second amplitude control means for producing a second preset amplitude; a fourth accumulator register having a parallel input and a serial output; means for gating the output of the second amplitude control means to the parallel input of the fourth accumulator register in alternate response to; the serial output of the first accumulator register until the parallel output of the down counter reaches zero, and the serial output of the second accumulator register until the parallel output of the down counter reaches zero; a second up-down counter having a parallel output and an input serially connected to the output of the fourth accumulator register; means for detecting a zero at the output of the second up-down counter; mEans for reversing the up-down mode of the first up-down counter in response to the zero detected at the output of the second up-down counter; means for detecting a zero at the output of the first up-down counter; means for reversing the up-down mode of the second up-down counter in response to the zero detected at the output of the first up-down counter; so that a sine wave will appear at the parallel of the first up-down counter and a cosine wave will appear at the parallel output of the second up-down counter.
 2. A digital signal generator as set forth in claim 1 and further including: means for disconnecting the serial input to the down counter; and means for constantly loading the down counter so that the serial output of the second accumulator is 0.707 times the clock rate; to produce a triangular wave at the parallel output of the first up-down counter. 